Reduced Wafer Warpage and Stress in Jsr Dielectric Films

The addition of polymer dielectric films to silicon wafers is useful in producing stress reduction layers and interconnect structures for chip-scale packaging as well as 3D wafer stacks. The use of lower cure temperature materials offers several advantages including a lowered thermal budget on devices that are sensitive to electrical performance change with temperature. Unfortunately, enough stress remains from the difference in the coefficients of thermal expansion of the polymer and the silicon to cause significant wafer bow and handling problems. This warpage problem increases as the wafers are thinned for 3D stacking, TSV, or are used in embedded system packaging. This work describes substantial stress and warpage reduction of positiveand negative-acting photo-dielectric films from JSR Micro, Inc.. Multi-step cure profiles using variable frequency microwaves (VFM) that include low temperature steps and very fast ramps were evaluated with statistical designs. The same materials were cured to the same extent (as measured by TMA and solvent resistance) using a standard convection oven for comparison. Large reductions of wafer warpage does not come at the expense of longer processing times but just the opposite. Substantially lowered cure temperatures and much faster cycle times are reported for these films. The results are discussed in terms of molecular and bulk curing mechanisms. INTRODUCTION The use of dielectric films after the last passivation layer on wafers has a long history [1]. The primary purpose of this additional organic film was as a stress buffer layer (SBL) between the high modulus silicon nitride (or oxide) and the high modulus epoxy molding compound or encapsulant that would be the typical covering to a wire-bonded die. This layer both planarizes and provides mechanical and alphaparticle protection. The SBL would typically be a low modulus polyimide coating of 2-5 micron thickness and be fully cured to obtain optimal mechanical and chemical protection of the die. At the end of the ‘90s, integrated passive devices produced at the wafer scale, introduced the addition of a second layer of dielectric film to re-distribute the die bond pads to peripheral bond pads [2]. This use of a re-distribution layer (RDL) has expanded to memory devices and grown in thickness to as much as 20 microns. Since most DRAM memory devices have two internal rows of pads, the new, larger, peripheral pads have enabled the stacking of thinned dice with overlapping or staggered wire-bonds (Figure 1). Figure 1: RDL layers leading to peripheral wire bonds An additional use of dielectric films is the direct application of at least two re-distribution layers to an array of dice that have been embedded in a thermoset base. The dielectric films are patterned to bring the signals up to pads or bumps that can be spread out to an area larger than the die [3]. Stacked die, stacked packages, and stacked array modules are increasing in production volumes due to the potential improved reliability and lowered costs. Through-silicon-via (TSV) technology has recently become a serious contender for stacked die in a very small form factor. In most versions of TSV there is a need for polymer films for dielectric isolation or for temporary or permanent adhesion. In all of these applications there has been an increasing concern about the warpage produced by the difference in thermal coefficient of expansion (CTE) of polymers (18-60 ppm/°C) and silicon (3 ppm/°C) during cure processes. In the case of polyimide SBL, the warpage from this one step accounts for a 100% increase over all previous processing [4] and causes serious handling problems especially for 300 mm wafers. That study also found increased warpage with larger numbers of dice per wafer and thicker dielectric layers. In addition, they found that reduced cure temperature, wait periods, and additional cure steps were not successful at reducing warpage. With increasing numbers of polymer layers in the applications described above and the thinning of wafers from 750 μm to less than 50 μm for stacking and TSV, warpage has become a serious issue. Warpage (and stress) can be reduced by lowering the largest temperature excursion from cure soak to ambient of the last process step. With multiple dielectric layer designs, the use of lower cure temperatures for early layers does not relieve the stress of the last high temperature cure. An incomplete cure at a lower temperature will reduce warpage but only if the die does not see any subsequent higher temperature processes such as solder reflow (260°C). Product reliability failures caused by incomplete cure and increased stress by later thermal processing are well known [5]. Very slow ramp rates to final soak temperature and slow cooling ramp rates are commonly used to reduce film stress but the effect is relatively small and the total cycle time increases from 1 hour to 4-10 hours which reduces throughput dramatically. Less than fully cured PI and PBO films will continue to release water (from the cyclization reaction) as the films are heated during additional processing steps, bonding, and solder reflow during assembly. Less than fully cured epoxies, resists, and other cross-linked polymers will continue to cure during subsequent processing which will change the glass transition temperature (Tg) of the films. The Tg is the point at which dramatic changes in the film’s modulus, elongation and coefficient of thermal expansion occur. These films will continue to shrink in the solid phase as they continue to cure during later treatments. Cracks form that are not initially found because they are the result of the additional curing of the layers that are no longer visible in a stack. Of course incompletely cured films will also form cracks with exposure to process chemicals such as acetone, NMP, developers, and strippers (Figure 2) [6]. Figure 2: Film cracking from incomplete cure An alternative curing technology using variable frequency microwaves (VFM) has begun moving to wafer production recently, to provide faster and lower temperature wafer dielectric cure [7,8]. Standard convection heat curing is a sequence of heat transfer from either coils or infra-red emitters to air to the target parts, the oven walls and the fixtures. Even though microwave heating is a thermal process, the fundamental mechanism is based on the excitement of molecular dipoles in the polymer resin and their subsequent dielectric loss to molecular rotations [9]. This direct increase in the entropy of the system at each molecular dipole site causes more rapid collisions of reacting molecules at the proper reaction orientation at a effective lower bulk temperature of the material. The VFM technology was developed to prevent the arcing of metals and to provide a uniform energy field particularly for use in microelectronics production processes. Many studies by semiconductor fabricators have shown no effect of VFM on the electrical or structural characteristics of semiconductor devices. It would be expected that VFM curing would provide lower warpage films from the inherent properties of the microwave heating process. Since the entire bulk of the dielectric film layer is heated simultaneously, the uniformity of the cure should be good from top to bottom and center to edge of the wafer. It has been shown that even in batch microwave systems, the uniformity of cure across a 300 mm wafer and from wafer to wafer in the stack is less than 2%. Previously unpublished studies have found the expected reduced warpage from VFM curing compared to standard furnace cures (Figure 3).